Integrated circuit with a reduced risk of punch-through between buried layers, and fabrication process

ABSTRACT

The semiconductor substrate of the integrated circuit includes at least one dielectrically isolating, vertical buried trench ( 2 ) having a height at least five times greater than its width, the trench laterally separating two regions ( 4, 5 ), and an epitaxial semiconductor layer ( 6 ) coveting the trench. An application is advantageously suited to MOS, CMOS and BiCMOS technologies.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is the National Stage of International Application No.PCT/FR02/00055 filed on Jan. 9, 2002, which is based upon and claimspriority from prior French Patent Application No. 0100412 filed Jan. 12,2001, the entire disclosure of which is herein incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the fabrication of integrated circuits.It is more particularly appropriate for the production of MOS orcomplementary MOS devices or the fabrication of bipolar transistors andcomplementary MOS transistors (BiCMOS) in the same semiconductorsubstrate.

2. Description of Related Art

In the fabrication of bipolar or MOS components, buried layers arefirstly formed in the semiconductor substrate, generally made ofsilicon, these buried layers subsequently playing a specific roleaccording to the component produced. Thus, the buried layers mayespecially be collectors for bipolar transistors, or else well bottomcontacts for MOS transistors. These buried layers are characterized bytheir p-type or n-type doping so as to meet the specificities of thecomponents that it is desired to produce (an npn or pnp bipolartransistor or an nMOS or pMOS transistor). Within the same semiconductordevice, it is possible to encounter two adjacent MOS transistors ofdifferent conductivity (CMOS), two adjacent MOS transistors of the sameconductivity separated by a region of opposite conductivity, and MOStransistors and bipolar transistors (BiCMOS).

Although being constituent elements of separate components, the buriedlayers within the same substrate cannot be doped independently of oneanother. This is because the doping levels of the buried layersdetermine, in particular, parasitic phenomena such as the breakdownvoltage between p-type and n-type layers, and the punch-through voltagebetween layers of the same type of conductivity.

Thus, for example, the breakdown voltage between two layers of oppositeconductivity is lower the greater the doping gradient between theselayers. This is generally the case when the buried layers are highlydoped.

Moreover, the risk of punch-through between buried layers of the sametype is higher the shorter the distance separating the two layers. Theseparating region of opposite conductivity, which is not highly dopedand is becoming narrower and narrower, can no longer fulfil its role ofproviding isolation between the two buried layers of the same type. Theminiaturization of the integrated circuits necessarily leads to anincrease in this risk.

To remedy the problem of punch-through, it would be conceivable toreduce the doping level of the layers of the same kind and increase thatof the layers of opposite conductivity which separate them. This wouldin particular have the consequence of limiting the diffusion of thedopants from the highly doped layers into the lightly doped isolatinglayers. However, modification of the doping levels of the buried layerswould also modify the intrinsic operation of the desired devices.Furthermore, if the doping of the separating layers is increased, thereis also a risk of lowering the breakdown voltages.

With the reduction in size of the components and integrated circuits, itwill become increasingly complicated to obtain a satisfactory compromisebetween the intrinsic operation of the devices and their isolation.

There is therefore a need to overcome these parasitic phenomena causedby the proximity of the components, and especially the contiguity of theburied layers.

More particularly, it seems to be necessary to provide solutions forminimizing, or indeed eliminating, the risk of punch-through of theburied layers and the lowering of the breakdown voltages, while stillmaintaining the proper intrinsic operation of the components produced.

SUMMARY OF THE INVENTION

The Applicant provides a solution which allows these problems to beremedied.

The invention essentially consists of the formation of buried trencheswhich laterally isolate, from one another, the buried layers ofidentical or different conductivities. In particular, it has been foundthat it is possible to prevent the immediate punch-through of the buriedlayers by adding such trenches in the semiconductor substrate betweenthe layers. These trenches are positioned so as to separate the buriedlayers of different or identical conductivity from one another. Thesetrenches form an obstacle to the diffusion of the dopants from oneburied layer to another, and they also reduce the risk of lowering thebreakdown voltage.

The proper intrinsic operation of the components is ensured because ofindependent doping of the buried layers of the device.

Thus, the invention provides an integrated circuit comprising asemiconductor substrate, for example made of silicon, including at leastone dielectrically isolating, vertical buried trench having a height atleast five times greater than its width, said trench laterallyseparating two regions, and an epitaxial semiconductor layer, forexample made of single-crystal silicon, covering said trench.

The trenches prevent the diffusion of dopants through them, or elseensure galvanic isolation.

The trench must be narrow enough to allow the growth of a homogeneousepilayer over the entire surface of the semiconductor wafer. Preferably,the width of these trenches is less than 1 μm, more preferably less than0.3 μm and more particularly about 0.2 μm.

The depth of the trenches may vary depending on the requirement of thesemiconductor device produced within the substrate.

As an indication, a trench may have a width of 0.2 microns and a heightof greater than 5 microns, and may be buried at a depth of at least 0.8microns.

Advantageously, the invention applies when there are at least three n, pand n or p, n and p adjacent buried layers, especially when it isdesired to produce two MOS transistors of the same kind, the buriedlayers of which are separated by a region of opposite conductivity, orelse in the case of BiCMOS technology since, in this situation, the riskof immediate punch-through of the buried layers may be high. Theformation of narrow trenches, in order to laterally isolate the buriedlayers from one another, allows this risk to be greatly reduced or eveneliminated.

Thus, according to one embodiment, the substrate includes at least twoburied trenches and at least three adjacent buried regions ofalternating conductivity, each of these buried regions being laterallyseparated from the region which is adjacent to it by a trench.

The substrate may include, approximately above the three buried regionsof alternating conductivity, three epitaxial regions, having the sametypes of conductivity as the three buried regions respectively, and thecircuit may include two MOS transistors of the same kind which areformed in the two epitaxial regions having the same type ofconductivity.

As a variant, the circuit may include two MOS transistors of differentkind which are formed in the two epitaxial regions having two differenttypes of conductivity, respectively.

It may also furthermore include a bipolar transistor formed in the thirdepitaxial region.

The subject of the invention is also a process for fabricating anintegrated circuit, comprising the formation of at least onedielectrically isolating, vertical buried trench in the semiconductorsubstrate of the circuit, said trench having a height at least fivetimes greater than its width and laterally separating two regions, andthe formation of an epitaxial semiconductor layer covering said trench.

The two regions may have conductivities of different type, which areobtained by implantation of dopants.

According to one method of implementation:

a) said trench is formed in the substrate;

b) the two regions having the same type of conductivity or else havingtwo different types of conductivity are formed on each side of thetrench by implantation;

c) an annealing operation is carried out; and

d) said epitaxial layer is grown, by epitaxy, on the structure obtainedin step c).

The trench is preferably formed before the implantation of dopants inthose regions of the substrate which are intended to subsequently formthe buried layers. This is because, after this moment in the process,the thermal budget is less but there is less of a risk of the dopantsdiffusing from one layer to another. However, it may be envisaged toetch the trenches after implantation in specific cases that couldrequire certain devices.

This implantation step is usually followed by an annealing operation inorder to make the dopants diffuse, particularly over a thickness ofpreferably less than the depth of the trenches.

According to one method of implementation, a first single-crystalsilicon layer is then grown epitaxially over the entire surface of thesubstrate. The very small size of the trenches allows almost homogeneoussingle-crystal silicon growth over the entire surface of the substrate.

It is possible to form, in this epitaxial single-crystal silicon layer,regions of the same conductivity as those of the subjacent buried layersand it is then advantageous to carry out an annealing operation so thatthere is continuity between the dopant in this epitaxial region and thatin the buried region.

According to one method of implementation, prior to step b), thetrenches are filled with a dielectric, preferably silicon oxide. Itwould also be possible to use nitride compounds or “insulator+conductor”compounds such as, for example, silicon dioxide+polysilicon.

The process of the invention may advantageously be implemented in orderto produce contiguous MOS and/or bipolar transistors, especially inBiCMOS and CMOS technologies.

BRIEF DESCRIPTION OF THE DRAWINGS

The rest of the description refers to the appended figures, respectivelyFIGS. 1a to 1 d, which show schematically the main steps of particularmethods of implementing the process of producing a semiconductor deviceincorporating narrow buried trenches according to the invention. Theseparticular methods of implementation of the process of the invention arein no way limiting.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The integrated circuit produced according to the methods ofimplementation illustrated in FIGS. 1a to 1 b includes componentsrequiring contiguity of three buried layers, the central one of whichhas a first type of conductivity and two lateral ones have a second typeof conductivity. Of course, the invention is not limited to thisparticular situation, rather it also encompasses especially thecontiguity of two buried layers of different conductivity or thecontiguity of more than three buried layers.

According to the process of the invention, the position on asemiconductor substrate 1, generally made of silicon, of the variousregions of implantation of n- or p-type dopants, these regionssubsequently forming the buried layers, is determined beforehand in aconventional manner.

According to a preferred method of implementing the process of theinvention, and as illustrated in FIG. 1a, trenches 2 are then etched atthe position of the junctions between these various regions. Thesetrenches 2 may be deep or shallow. Their size depends essentially on thesubsequent implantation and the thickness of the buried layers, on theannealing operations and therefore, more generally, on the componentthat it is desired to produce.

If their depth can vary, the width of the trenches 2 constitutes animportant parameter. This is because the trenches 2 must be wide enoughso that, on the one hand, they can be formed technically and can befilled uniformly with a dielectric and, on the other hand, they canfulfil their role of providing isolation between two layers of differentconductivity. Furthermore, the trenches 2 must be narrow enough to allowthe growth of a homogeneous epitaxial layer of single-crystal siliconover the entire surface of the wafer.

The width of the trenches 2 according to the process of the invention ispreferably less than 1 μm and even more preferably less than 0.3 μm.More particularly, according to one preferred method of implementing theinvention, the trenches 2 have a width of about 0.2 μm.

Next, the trenches 2 are filled with a dielectric 3. It will bepreferable to use silicon oxide as isolating material in the trenches.

As illustrated in FIG. 1b, regions of different conductivity are thenformed on each side of the trenches. In the device illustrated in FIG.1b, a region 5 of a first type of conductivity is formed between the twotrenches 2. On the other side of the trenches 2, or else on the outsideof the trenches 2, two regions 4 of a second type of conductivity havebeen formed. The doping of these regions is carried out conventionally,by ion implantation with suitable dopants (for example).

In FIG. 1b, the central region is of p-type conductivity and the lateralregions are of n-type conductivity. Conductivities which are theopposite of these regions also fall within the scope of the process ofthe invention. The regions 4 and 5 will constitute the buried layers ofthe semiconductor components produced. These buried layers may, forexample, be collectors for bipolar transistors or else well bottomcontacts for MOS transistors.

After doping, the process generally continues with a thermal annealingoperation so that the implantation regions 4 and 5 extend, inparticular, over the entire desired thickness and preferably over athickness of less than the depth of the trenches 2.

According to a preferred method of implementing the invention, theisolating trenches are formed before implantation of the buried layersso as to prevent any diffusion of dopants from one region to another,especially during the annealing step.

At this step of the process of the invention, the regions of differentconductivity are separated from one another by isolating trenches, asillustrated in FIG. 1b. The lateral diffusions of the regions 4 and 5are limited. There is no compensating of the dopants between thesevarious regions. Furthermore, the highly doped parts are no longer incontact with one another, as they would be previously without thetrenches. A dielectric wall separates the highly doped buried layers,which results in an increase in the breakdown voltages and therefore ahigher performance of the semiconductor components produced.

Moreover, according to the process of the invention, it is now possibleto dope the buried layers independently of one another, thereby addingan additional degree of freedom in the production of components. This isbecause the choice of doping level now depends only on the nature of thecomponents that it is desired to produce and it respects their intrinsicoperation.

A first single-crystal silicon layer 6 is then grown epitaxially overthe entire wafer. This layer 6 grows on the surface of the substrate 1and of the trenches 2 by vertical and lateral epitaxial growth.

As illustrated in FIG. 1c, implantations in this first epitaxial layer6, and approximately above each of the regions formed in the previousstep, are then produced in order to form regions of the sameconductivity. Thus, the layer 8 is of the first type of conductivity andthe layers 7 are of the second type of conductivity, corresponding tothe layers 5 and 4 respectively.

After this implantation, a thermal annealing operation is carried out sothat the layers 7 and 8 extend in particular over the entire thicknessof the epitaxial layer 6.

As illustrated in FIG. 1d, the doping operations were carried out sothat the central region 8 is p-doped and the lateral regions 7 aren-doped. The doping of the epitaxial layer depends on the conductivityof the buried layers or on the semiconductor device to be produced. Theopposite conductivity to the situation illustrated also falls within thescope of the invention.

According to the process of the invention, the desired semiconductorcomponents are then formed in the epitaxial layers of differentconductivity using standard processes.

As an entirely nonlimiting example, it may be envisioned to produceseveral types of semiconductor devices from the device illustrated inFIG. 1d.

According to a first variant, two pMOS transistors may be produced inthe n-type epitaxial regions 7. The n-doped buried layers 4 thenconstitute the well bottom contacts for these transistors. The centralp-type region constitutes a separating region of opposite conductivity.

According to another variant, it may be envisioned to produce a pMOStransistor on an epitaxial region 7 in the same way. In the other,n-doped, epitaxial region 7, it may be envisioned to produce an npnbipolar transistor, in which case the n-type buried layers 4 willconstitute the well bottom contact of the MOS transistor and thecollector of the bipolar transistor, respectively. The p-doped centralregion consisting of the layers 5 and 8 may then serve as base for theproduction of an nMOS transistor.

These various devices are isolated from one another by the junction 20and by the depthwise dielectric isolation 3.

The process of the invention is particularly suitable for the productionof transistors in MOS, CMOS or BiCMOS technology.

The semiconductor devices produced according to the process of theinvention exhibit better breakdown behavior and a considerably reduced,if not nonexistent, immediate punch-through of the buried layers isobserved.

The invention also applies to power devices, by allowing depthwisedielectric isolation.

It also applies to sensor devices, preventing lateral leakage currentsfrom deep junctions.

What is claimed is:
 1. An integrated circuit comprising: a semiconductorsubstrate, wherein the semiconductor substrate includes: at least onetrench, being dielectrically isolating, vertically buried, and having aheight at least five times greater than its width, and wherein each ofthe at least one trench laterally separating two regions (4, 5) of thesemiconductor substrate; and an epitaxial semiconductor layer coveringthe at least one trench.
 2. The integrated circuit according to claim 1,wherein the semiconductor substrate is formed from single-crystalsilicon.
 3. The integrated circuit according to claim 2, wherein thesemiconductor substrate includes at least two buried trenches and atleast three adjacent buried regions of alternating conductivity, each ofthese buried regions being laterally separated from the region which isadjacent to it by a trench.
 4. The integrated circuit according to claim1, wherein the width of the trench is less than 0.3 microns.
 5. Theintegrated circuit according to claim 1, wherein the two regions havingconductivities of different type.
 6. The integrated circuit according toclaim 5, wherein the width of the trench is less than 0.3 microns. 7.The integrated circuit according to claim 5, wherein the semiconductorsubstrate is formed from single-crystal silicon.
 8. The integratedcircuit according to claim 7, wherein the width of the trench is lessthan 0.3 microns.
 9. The integrated circuit according to claim 7,wherein the trench has a width of 0.2 microns and a height of greaterthan 5 microns and in that it is buried at a depth of at least 0.8microns.
 10. The integrated circuit according to claim 1, wherein thesemiconductor substrate includes at least two buried trenches and atleast three adjacent buried regions of alternating conductivity, each ofthese buried regions being laterally separated from the region which isadjacent to it by a trench.
 11. The integrated circuit according toclaim 10, wherein the substrate includes, approximately above the threeburied regions of alternating conductivity, three epitaxial regions,having the same types of conductivity as the three buried regionsrespectively, and in that the circuit includes two MOS transistors ofthe same kind which are formed in the two epitaxial regions having thesame type of conductivity.
 12. The integrated circuit according to claim10, wherein the substrate includes, approximately above the three buriedregions of alternating conductivity, three epitaxial regions, having thesame types of conductivity as the three buried regions respectively, andin that the circuit includes two MOS transistors of different kind whichare formed in the two epitaxial regions having two different types ofconductivity, respectively.
 13. The integrated circuit according toclaim 12, further comprising a bipolar transistor formed in the thirdepitaxial region.
 14. A process for fabricating an integrated circuit,comprising the steps of: forming at least one dielectrically isolating,vertically buried trench in a semiconductor substrate of an integratedcircuit, each of the at least one trench having a height at least fivetimes greater than its width and laterally separating two regions of thesemiconductor substrate; and forming an epitaxial semiconductor layercovering the at least one trench.
 15. The process according to claim 14,wherein the width of the at least one trench is less than 0.3 microns.16. The process according to claim 14, wherein the semiconductorsubstrate being made of silicon: a) the at least one trench is formed inthe semiconductor substrate; b) the two regions having conductivity ofone of the same type of conductivity for the two regions and twodifferent types of conductivity for the two regions, and being formed oneach side of the at least one trench by implantation; c) an annealingoperation being carried out; and d) the epitaxial layer being grown, byepitaxy, on the structure obtained in step c).
 17. The process accordingto claim 16, wherein prior to step b) each of the at least one trench isfilled with a dielectric, preferably silicon oxide.
 18. The processaccording to claim 14, wherein the two regions have conductivities ofdifferent type, which are obtained by implantation of dopants.
 19. Theprocess according to claim 18, wherein the width of the at least onetrench is less than 0.3 microns.
 20. The process according to claim 18,wherein the semiconductor substrate being made of silicon: a) the atleast one trench is formed in the semiconductor substrate; b) the tworegions having different types of conductivity for the two regions, andbeing formed on each side of the at least one trench by implantation; c)an annealing operation being carried out; and d) the epitaxial layerbeing grown, by epitaxy, on the structure obtained in step c).
 21. Theprocess according to claim 20, wherein prior to step b) each of the atleast one trench is filled with a dielectric, preferably silicon oxide.22. The process according to claim 14, wherein at least two buriedtrenches and at least three adjacent buried regions of alternatingconductivity are formed in the substrate, each of these buried regionsbeing laterally separated from the region which is adjacent to it by atrench, and in that three epitaxial regions are formed in the epitaxiallayer, approximately above the three buried regions of alternatingconductivity, these epitaxial regions having the same types ofconductivity as the three buried regions respectively.
 23. The processaccording to claim 22, wherein two MOS transistors of the same kind areformed in the two epitaxial regions having the same type ofconductivity.
 24. The process according to claim 22, wherein two MOStransistors of different kind are formed in the two epitaxial regionshaving two different types of conductivity, respectively.
 25. Theprocess according to claim 24, wherein a bipolar transistor isfurthermore formed in the third epitaxial region.